//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// The confidential and proprietary information contained in this file may     
// only be used by a person authorised under and to the extent permitted       
// by a subsisting licensing agreement from ARM Limited.                       
//                                                                             
//            (C) COPYRIGHT 2005-2013 ARM Limited.
//                ALL RIGHTS RESERVED                                          
//                                                                             
// This entire notice must be reproduced on all copies of this file            
// and copies of this file may only be made by a person if such person is      
// permitted to do so under the terms of a subsisting license agreement        
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//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Top-Level Verilog file is auto-generated by AMBA Designer ADr3p4-00rel0-build-0086
//                                                                             
// Stitcher: generic_stitcher_core v3.1, built on Sep 18 2013
//                                                                             
// Filename: nic400_cd_clk_aud_12288k_ysyx_rv32.v
// Created : Mon May 27 20:11:37 2024                            
//                                                                             
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Generated with Validator version0.1


//-----------------------------------------------------------------------------
// Module Declaration nic400_cd_clk_aud_12288k_ysyx_rv32
//-----------------------------------------------------------------------------

module nic400_cd_clk_aud_12288k_ysyx_rv32 (
  
// Instance: u_tpv_gp_apb4_i2s_slv_apb4_bmd_async, Port: apb4_m

  paddr_i2s_slv_apb4,
  pwdata_i2s_slv_apb4,
  pwrite_i2s_slv_apb4,
  pprot_i2s_slv_apb4,
  pstrb_i2s_slv_apb4,
  penable_i2s_slv_apb4,
  pselx_i2s_slv_apb4,
  prdata_i2s_slv_apb4,
  pslverr_i2s_slv_apb4,
  pready_i2s_slv_apb4,
  
// Instance: u_tpv_gp_apb4_i2s_slv_apb4_bmd_async, Port: apb_int_async

  preq_i2s_slv_apb4_int_master_async,
  pack_i2s_slv_apb4_int_master_async,
  pfwdpayld_i2s_slv_apb4_int_master_async,
  prevpayld_i2s_slv_apb4_int_master_async,

//  Non-bus signals

  clk_aud_12288kclk,
  clk_aud_12288kclken,
  clk_aud_12288kresetn

);



//-----------------------------------------------------------------------------
// Port Declarations
//-----------------------------------------------------------------------------


// Instance: u_tpv_gp_apb4_i2s_slv_apb4_bmd_async, Port: apb4_m

output [31:0] paddr_i2s_slv_apb4;
output [31:0] pwdata_i2s_slv_apb4;
output        pwrite_i2s_slv_apb4;
output [2:0]  pprot_i2s_slv_apb4;
output [3:0]  pstrb_i2s_slv_apb4;
output        penable_i2s_slv_apb4;
output        pselx_i2s_slv_apb4;
input  [31:0] prdata_i2s_slv_apb4;
input         pslverr_i2s_slv_apb4;
input         pready_i2s_slv_apb4;

// Instance: u_tpv_gp_apb4_i2s_slv_apb4_bmd_async, Port: apb_int_async

input         preq_i2s_slv_apb4_int_master_async;
output        pack_i2s_slv_apb4_int_master_async;
input  [71:0] pfwdpayld_i2s_slv_apb4_int_master_async;
output [32:0] prevpayld_i2s_slv_apb4_int_master_async;

//  Non-bus signals

input         clk_aud_12288kclk;
input         clk_aud_12288kclken;
input         clk_aud_12288kresetn;



//-----------------------------------------------------------------------------
// Internal Wire Declarations
//-----------------------------------------------------------------------------

wire           pack_i2s_slv_apb4_int_master_async;
wire   [31:0]  paddr_i2s_slv_apb4;
wire           penable_i2s_slv_apb4;
wire   [2:0]   pprot_i2s_slv_apb4;
wire   [32:0]  prevpayld_i2s_slv_apb4_int_master_async;
wire           pselx_i2s_slv_apb4;
wire   [3:0]   pstrb_i2s_slv_apb4;
wire   [31:0]  pwdata_i2s_slv_apb4;
wire           pwrite_i2s_slv_apb4;
wire           clk_aud_12288kclk;
wire           clk_aud_12288kclken;
wire           clk_aud_12288kresetn;
wire   [71:0]  pfwdpayld_i2s_slv_apb4_int_master_async;
wire   [31:0]  prdata_i2s_slv_apb4;
wire           pready_i2s_slv_apb4;
wire           preq_i2s_slv_apb4_int_master_async;
wire           pslverr_i2s_slv_apb4;



//-----------------------------------------------------------------------------
// Sub-Modules Instantiation
//-----------------------------------------------------------------------------

nic400_apb_bridge_master_domain_ysyx_rv32     u_tpv_gp_apb4_i2s_slv_apb4_bmd_async (
  .paddrm               (paddr_i2s_slv_apb4),
  .pwdatam              (pwdata_i2s_slv_apb4),
  .pwritem              (pwrite_i2s_slv_apb4),
  .penablem             (penable_i2s_slv_apb4),
  .pselm                (pselx_i2s_slv_apb4),
  .prdatam              (prdata_i2s_slv_apb4),
  .pclkm                (clk_aud_12288kclk),
  .pclkenm              (clk_aud_12288kclken),
  .presetmn             (clk_aud_12288kresetn),
  .pslverrm             (pslverr_i2s_slv_apb4),
  .preadym              (pready_i2s_slv_apb4),
  .pprotm               (pprot_i2s_slv_apb4),
  .pstrbm               (pstrb_i2s_slv_apb4),
  .apbs_req_async       (preq_i2s_slv_apb4_int_master_async),
  .apbs_ack_async       (pack_i2s_slv_apb4_int_master_async),
  .apbs_fwd_data_async  (pfwdpayld_i2s_slv_apb4_int_master_async),
  .apbs_rev_data_async  (prevpayld_i2s_slv_apb4_int_master_async)
);



endmodule
